1. Field of the Invention
This invention relates to a pulse generator for producing a pulse whose width can be set arbitrarily corresponding to given data. In particular, this invention relates to a pulse generator which can be used in a PWM (Pulse Width Modulation) system, and which is able to deal with a reference clock signal having a high frequency.
2. Description of the Prior Arts
FIG. 5 is a schematic diagram showing one prior art pulse generator of this invention. The pulse generator produces a pulse whose pulse width can be set arbitrarily corresponding to given data. FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 5. In this timing chart, N, which shows the bit number of input data as shown in FIG. 5, is set to 4, that is, N=4.
As shown in FIG. 5, the conventional pulse generator is comprised of the following: a presetting clock synchronous up-counter (referred to as a counter, below) 101 having a count-enable terminal; equality comparators 102 and 103, each of which compares binary data A (input A) of N bits with data B (input B) of N bits, and generates a level H signal from its output EQ when A=B; OR gates 104 and 105; an AND gate 106; and a T-type flip flop 107. The bit number of counter 101 can be set arbitrarily. In this case, a 4 bit counter is chose as an example. In other words, clock signal CLK 1 is input to this pulse generator in order to activate 4 bit up-counter 101. The basic unit of time width of this clock signal CLK 1 is equal to its one period.
In the case where the pulse having a pulse width of 4 .mu. s is required in said device, 4.sub.16 should be given as input data D and a clock signal having a 1 MHz frequency (its one period is equal to 1.mu.s) is given as clock signal CLK 1. The subscripts 16 mean that the number 4 is a hexadecimal digit.
In the circuit shown in FIG. 5, enable terminal EN in counter 101 is set to an assert state to allow counter 101 to count up. When equality comparator 102 finds that output CO of counter 101 reaches 0 (that means the beginning of counting up), it sets output EQ 1 to level H. Similarly, when equality comparator 103 finds that output CO of counter 101 reaches the same number as that of input data D, that is 4 in this case, it sets output EQ 2 to level H. Thereafter, OR gate 105 calculates the logical sum of signals EQ 1 and EQ 2 so as to produce clock signal CLK 2. A pulse P having a 4.mu.s pulse width is obtained from this clock signal CLK 2 through T-type flip flop 107.
OR gate 104 is provided in order to fix clock signal CLK 2 to level L when input data D is equal to 0.sub.16, thus interrupting the output of pulse P. This is because that no pulse should be output from T-type flip flop 107, when data D is set to 0.sub.16 (pulse width=0).
In the above mentioned pulse generator, the following problems arise.
(1) Requires a large scale circuit
The circuit scale of this device becomes larger in proportion to bit number N of input data D. In other words, when N becomes larger, larger scales of counter 101, equality comparators 102 and 103, and OR gate 104 should be used. As a result, the circuit becomes enormous in scale.
(2) Pulse width t.sub.pw2 of output pulse P being affected significantly by the time delay caused by gates.
In the timing chart shown in FIG. 6, pulse width t.sub.pw2 of output pulse P is determined based on to the transition points of output CO from counter 101. In actuality, the rising edge of pulse P contains three kinds of time delays t.sub.D1, t.sub.D3, and t.sub.D7 which occur from the time that counter output CO changes to 0.sub.16. Also, the falling edge of pulse P contains three kinds of time delay t.sub.D2, t.sub.D5, and t.sub.D8 which occur from the time that counter output CO changes to 4.sub.16. Thus, the rising edge and the falling edge of output pulse P are influenced respectively by three parameters. Among these, t.sub.D1 and t.sub.D2 caused by comparators 102 and 103 have quite large values as compared with the other parameters caused by gates, because equality comparators usually have a large delay time.
In addition, clock signal CLK 2, which is to be input to T-type flip flop 107, is obtained by calculating the logical product of clock signal CLK 1 and the output from comparator 102 or 103 using AND gate 106. As a result, if the sum of t.sub.D1 and t.sub.D3 becomes larger than the pulse width t.sub.pw1 of clock signal CLK 1, pulse H given by clock signal CLK 2 can't be output any more. For parameters t.sub.D2 and t.sub.D5, the same situation occurs. Accordingly, in order to operate this pulse generator adequately, the maximum operating frequency should satisfy the following conditions: EQU t.sub.pw1 &gt;t.sub.D1 +t.sub.D3, and EQU t.sub.pw1 &gt;t.sub.D2 +t.sub.D5.
As a result, the reference frequency of clock signal CLK 1 should be chosen within a few MHz.